The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including vertically stacked n-type field effect transistors (nFETs) containing an n-type work function metal gate and p-type field effect transistors (pFETs) containing a p-type work function metal gate, and a method of forming the same.
The use of non-planar semiconductor devices such as, for example, semiconductor fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. One type of non-planar semiconductor device that has been touted as a viable option beyond the 7 nm technology node is a nanosheet containing device. By “nanosheet containing device” it is meant that the device contains one or more layers of semiconductor channel material portions having a vertical thickness that is substantially less than its width.
Also, three dimensional (3D) integration by vertically stacking nFETs and pFETs is an attractive approach for 3 nm node and beyond area scaling. Such vertically stacking of nFETs and pFETs combined with nanosheet technology can benefit from device electrostatics control in addition to area scaling. One problem associated with prior art devices that contain a combination of vertically stacked nFETs and pFETs and nanosheet technology is that independent work functional control for nFETs and pFETs is not possible. There is thus a need for providing a method that combines vertically stacked nFETs and pFETs and nanosheet technology that can implement independent work function metal gates for the nFETs and pFETs.